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ISL5239
Pin Descriptions (Continued)
NAME
A<5:0>
CS
WR
RD
BUSY
TYPE
I
I
I
I
O
DESCRIPTION
6-bit address bus that operates with P<15:0>, CS, RD, and WR to write to and read from the devices internal
control registers. Bit 5 is the MSB.
Chip Select. (active low). Enables device to respond to μ P access by enabling read or write operations.
Write Strobe, (active low). The data on P<15:0> is written to the destination selected by A<5:0> on the rising
edge of WR when CS is asserted (low).
Read Strobe (Active Low). The data at the address selected by A(5:0) is placed on P<15:0> when RD is
asserted (low) and CS is asserted (low).
μ P Busy. (Active Low) Indicates that the μ P interface is busy. The device asserts BUSY during a read operation
to indicate that the output data on P<15:0> is not ready, and it asserts this signal during a write operation to
indicate that it is not available for another read or write operation yet.
EXTERNAL SERIAL INTERFACE
SERCLK
SERSYNC
SEROUT
SERIN
O
O
O
I
Serial Clock. Clock signal provided to external device for serial input and output, derived from rising edge of
CLK.
Serial Sync. Active high single-cycle pulse that is time coincident with the first sample of the 32-bit serial data
frame. Derived from by rising edge of CLK.
Serial Output. Output data bit for the serial interface. Derived from the rising edge of CLK.
Serial Input.Input data bit for serial interface. Derived from rising edge of CLK.
FEEDBACK INTERFACE
FB<19:0>
FBCLK
TRIGGER INTERFACE
TRIGIN
TRIGOUT
DATA INPUT
IIN<17:0>
QIN<17:0>
ISTRB
CLKOUT
I
I
I
O
I
I
I
O
Feedback Input Data. Parallel or serial data to be stored in the feedback memory. In parallel mode, all 20-
bits are stored on the rising edge of FBCLK. In serial mode, bit 0 is serial input data and bit 1 is serial sync,
sampled at the rising edge of FBCLK.
Input clock used for sampling the FB<19:0> pins.
Trigger input. Hardwired trigger source to be used to trigger an input/feedback capture. Sampled internally
with rising edge of CLK.
Trigger output. Indicated that the capture system has been triggered, either internally or externally.
I input data. Real component of the complex input sample when input format is parallel. Alternating real and
imaginary when input format is muxed. Selectable as 2’s complement or offset binary.
Q input data. Imaginary component of the complex input sample when input format is parallel. Unused in serial
input format.
I data strobe. (active high). Used in the muxed input format. When asserted, the input data buses contains valid
I data.
Input data clock. Output clock for the data source driving the IIN<17:0> and QIN<17:0> inputs. Input data
busses sampled on the rising edge of CLK that generates the rising edge of CLKOUT.
DATA OUTPUT
IOUT<17:0>
QOUT<17:0>
I
I
I output data. Real component of the complex output sample driven by the rising edge of CLK. Selectable as
2’s complement or offset binary.
Q output data. IMaginary component of the complex output sample driven by the rising edge of CLK. Selectable
as 2’s complement or offset binary.
TEST ACCESS
DCTEST
O
DC tree output. NAND tree output for DC threshold test. Do not connect for normal operation.
JTAG TEST ACCESS PORT
TMS
TDI
TCK
TRST
TDO
I
I
I
I
O
5
JTAG Test Mode Select. Internally pulled up.
JTAG Test Data In. Internally pulled up.
JTAG Test Clock.
JTAG Test Reset (Active Low). Internally pulled-up.
JTAG Test Data Out.
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